Configurable electronic device which is compatible with a configuration bitstream of a prior generation configurable electronic device

ABSTRACT

A configurable electronic device which is compatible with a configuration bitstream of a prior generation configurable electronic device. The configurable device has a first configurable domain which is configurable with the configuration bitstream of the prior generation device and a second configurable domain which is optionally configurable. To function as the prior generation configurable device, the configurable device is loaded with the bitstream of the prior generation configurable device. To utilize the second configurable domain, another bitstream is concatenated to the bitstream intended for the first configurable domain. In a first embodiment, a signal is utilized to indicate when the first configurable domain is full of configuration bits, thereby indicating that the second configurable domain may load forthcoming bits. In a second embodiment, the configuration bitstream for the first configurable domain includes a bit to indicate whether a successive configurable domain may load forthcoming bits.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application relates to and incorporates by reference U.S. Pat. No.5,426,379, entitled, "Field Programmable Gate Array with Built-inBitstream Data Expansion," filed on Jul. 29, 1994, by Stephen M.Trimberger and co-pending U.S. patent application Ser. No. 08/389,846Docket X-140! entitled "A Field Programmable Gate Array HavingProgramming Instructions in the Configuration Bitstream," filed on Feb.17, 1995, by Stephen M. Trimberger, both assigned to Xilinx, Inc. of SanJose, Calif.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to configurable electronicdevices and more particularly to a configurable electronic device thatis compatible with configuration data for a prior generationconfigurable device.

2. Discussion of Background Art

Configurable electronic devices can be implemented using severaloptions: discrete logic devices, often called small-scale integratedcircuits (SSI); programmable devices such as programmable logic arrays(PLAs) and programmable logic devices (PLDs); mask-programmed gatearrays and cell-based application specific integrated circuits (ASICs);and field programmable gate arrays (FPGAs).

FPGAs are general purpose programmable devices that are customized byend users. An FPGA basically consists of an array of configurable logicblocks (CLBs) embedded in a programmably configurable interconnectstructure and surrounded by programmably configurable I/O blocks (IOBs).An IOB allows signals to be driven off-chip or optionally brought ontothe FPGA into segments of the interconnect structure. An IOB cantypically perform other functions, such as tri-stating outputs andregistering incoming or out-going signals.

The configurable interconnect structure allows users to implementmulti-level logic designs in which the output signal of a first logicunit is input to a second logic unit, the output of the second logicunit is input to a third logic unit, etc.

An FPGA can have tens of thousands of logic gates operating at tens ofmegahertz. An FPGA is programmed by loading programming data into thememory cells which control the configurable logic blocks, I/O blocks,and interconnect structure. Further information about FPGAs is availablein "The Programmable Logic Data Book," copyright 1994 by Xilinx, Inc.,2100 Logic Drive, San Jose, Calif. 95124, which is incorporated hereinby reference.

Each configurable logic block in the FPGA can include configurationmemory cells for controlling the function performed by that logic block.These configuration memory cells can implement a lookup table andcontrol multiplexers and other logic elements such as XOR gates and ANDgates and their interconnections. The lookup table is a truth tablewhich implements a combinational logic function.

Each configurable logic block may be associated with an adjacent portionof the interconnect structure. The interconnect structure includesprogrammable interconnect points (PIPs) which control the wiringconnections in the programmable interconnect network of the FPGA. Aprogrammable interconnect point may be a pass transistor controlled by aconfiguration memory cell. Wire segments on each side of the passtransistor are connected or not depending on whether the transistor isturned on by its configuration memory cell.

Configuration consists of loading a bitstream containing program datainto the configuration memory cells which control the configurable logicblocks and I/O blocks of the FPGA. The configuration memory cells aretypically distributed in a two dimensional array on the FPGA. Thebitstream is typically loaded serially into the FPGA to minimize thenumber of pins needed for configuration and to reduce the complexity ofthe interface to external memory. The bitstream is broken into datapackets called frames. As each frame is received in the FPGA it isshifted through a frame register until the frame register is filled. Thedata in the frame register are then loaded in parallel into one row ofconfiguration memory cells of the memory array.

Following loading of the first frame register of data, a subsequentbitstream data frame is shifted into the FPGA frame register, andanother row of configuration memory cells in the array of CLBs isdesignated to be loaded with a frame of bitstream data. After all rowsof configuration memory cells are loaded, the FPGA generates a "FULL"signal which causes any additional bits sent to the FPGA to betransmitted as overflow bits to another FPGA which is daisy-chained tothe FPGA (Id. at 2-32 through 2-41 and 2-126).

As an FPGA product line goes through its product life cycle, later FPGAversions are typically upgraded to extend the functionality of previousFPGA versions. For example, an upgraded FPGA may have user writablememory, whereas the original version does not; or a later FPGA may addcarry logic. Designers of original FPGAs cannot anticipate all featuresthat will be added in subsequent versions.

Maintaining bitstream compatibility through FPGA product line upgradesis important. Upgraded FPGAs should be able to accept bitstreams forprior version FPGAs so that users will not need to generate newbitstreams. However, programming additional features in subsequent FPGAversions requires using extra bits in the configuration memory. Asadditional bit locations in the configuration memory cells are required,one practice is to expand the frame register to accommodate theadditional bit locations. The problem with expanding the frame registeris that the later version and the original version of the FPGA are notbitstream compatible because different length bitstreams are used toprogram the original version and the later version.

An additional motivation for maintaining bitstream compatibility is thatit may be advantageous to produce only later versions of an FPGA andcease production of earlier versions. By maintaining bitstreamcompatibility, later versions of an FPGA product line can replaceearlier versions, suppliers can reduce their inventories ofdifferent-version FPGAs, and users of earlier versions will not need togenerate new bitstreams. Bitstream compatibility reduces the effortrequired to move from a prior generation to a present generation ofconfigurable device.

Therefore, an apparatus and method are needed to make a prior generationconfigurable device configuration bitstream compatible with a latergeneration configurable device.

SUMMARY OF THE INVENTION

The present invention provides an apparatus and a method to make apresent generation configurable electronic device that can use priorgeneration device configuration bitstreams. If additional features arerequired in the present generation device they may be configured byconcatenating additional bitstreams to the bitstream of the priorgeneration configurable device. The invention may also be utilized tomake a present generation configurable device compatible with a nextgeneration configurable device.

The invention contemplates that a prior generation configurable devicehas a "configurable domain," which is a group of memory cells thatcontrol a set of configurable logic blocks of the configurable device.

The prior generation configurable device is configurable with a "first"bitstream of bits which are loaded into the memory cells of the device.

The present generation configurable device has multiple configurabledomains. The first configurable domain is configurable to functionidentically to the configurable domain of the prior generation device.The additional configurable domains in the present generation device maybe optionally configured if the new features are desired.

To configure only the first configurable domain in the presentgeneration device, only the first bitstream is loaded into the firstconfigurable domain. To configure the additional configurable domains,additional bitstreams are concatenated to the first bitstream and loadedinto the respective configurable domains.

The configuration of the present generation configurable device isaccomplished as follows. A bitstream for configuring the presentgeneration device is loaded serially into the device. The firstconfigurable domain is the first to receive the configuration bits.Additional configuration bitstreams are transmitted to the additionalconfigurable domains. Each additional configurable domain is seriallyconnected to the preceding configurable domain for receiving thebitstream.

The first configurable domain loads the first bitstream into its memorycells. The first configurable domain has a control logic circuit whichindicates when all of its memory cells have been loaded. When the firstconfigurable domain is full, the next bitstream, if present, istransmitted to the second configurable domain. The second configurabledomain also has a control logic circuit for indicating when the bitsfrom its intended bitstream have all been loaded. Each of theconfigurable domains has a control logic circuit for indicating whenloading of the respective bitstream is complete.

In another aspect of the invention, each configuration bitstream has abit for indicating whether to utilize an additional configurable domainin the configurable device. This extension bit, together with thecontrol logic circuit that signals when loading of a bitstream iscomplete, provides a mechanism for bypassing later configurable domainswithin a configurable device.

The present invention is advantageous over an addressing mechanismbecause the invention minimizes circuitry required to select aconfigurable domain into which to load a bitstream. The invention isadvantageous over a structure that requires a large bitstream for alarge device no matter what use is made of the larger device because amultitude of extra unused bits in the configuration bitstream are notrequired for adapting the bitstream to a present generation configurabledevice. These and other advantages will be recognized in the teachingsset forth in the following description and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a block diagram illustrating a preferred embodiment of anapparatus for making the configuration bitstream of a prior generationconfigurable device compatible with a present generation configurabledevice;

FIG. 2 is a block diagram illustrating a configuration bitstream forconfiguring the device of FIG. 1;

FIG. 3 is a block diagram illustrating an alternative embodiment of anapparatus for making the configuration bitstream of a prior generationconfigurable device compatible with a present generation configurabledevice;

FIG. 4 is a block diagram illustrating a configuration bitstream forconfiguring the device of FIG. 3;

FIG. 5 is a block diagram illustrating a second alternative embodimentof an apparatus for making the configuration bitstream of a priorgeneration configurable device compatible with a present generationconfigurable device;

FIG. 6 is a flowchart of a preferred method for making the configurationbitstream of a prior generation configurable device compatible with apresent generation configurable device; and

FIG. 7 is a flowchart of an alternative method for making theconfiguration bitstream of a prior generation configurable devicecompatible with a present generation configurable device.

DETAILED DESCRIPTION

FIG. 1 is a block diagram illustrating an embodiment of a presentgeneration device having a bitstream compatible with the configurationbitstream of a prior generation configurable device. The apparatus ofFIG. 1 includes a first configurable domain 102, a second configurabledomain 104, a third configurable domain 106, an input line 108, a firstoverflow line 110, a second overflow line 112, a third overflow line114, and an interconnection matrix 116. A configurable domain is afunctional section of an FPGA which is configurable with a dedicated setof contiguous bits in a configuration bitstream. Interconnection matrix116 includes line segments and programmable interconnection points(PIPs) if necessary for interconnecting the domains.

The first configurable domain 102 is configured by configuration bitsreceived through input line 108. The configuration bitstream begins witha bit having a logic level `1`. All data preceding the first logic level`1` bit are ignored. After the first configurable domain 102 is full ofconfiguration bits, AND gate 146 allows any extra or "overflow"configuration bits to pass over the first overflow line 110 to thesecond configurable domain 104. The 2nd and 3rd configurable domains andmatrix 116 are programmed similarly to the first configurable domain102. The second configurable domain 104 receives as input the overflowbits received on the first overflow line 110 and the third configurabledomain 106 receives as input the overflow bits received on the secondoverflow line 112. After the third configurable domain 106 has beenprogrammed, any remaining overflow bits are output on the third overflowline 114 and may be used to program another configurable device (notshown).

Depending upon the capabilities of device 100 and requirements of theapplication, each configurable domain 102, 104, 106 may be programmed toperform different functions and to uniquely interface via theinterconnection matrix 116 with the other configurable domains 102, 104,106. While FIG. 1 shows the interconnection matrix 116 generally coupledto each configuration memory array 118, 119, 120, the interconnectionmatrix 116 includes any interconnect lines and PIPs necessary tointerface every IOB, CLB, or CL in the first configurable domain 102with every other IOB, CLB, or other structure in the second and thirdconfigurable domains 104 and 106. Such an interconnection capability maybe formed as a non-programmable structure, but a programmableinterconnection structure permits various custom-tailored interfacesbetween the configurable domains 102, 104, 106 as programmed by theconfiguration bits.

In FIG. 1, the first configurable domain 102 represents those functionsprovided in an earlier generation device. The second and third domains104 and 106 represent functions provided in the present device that werenot provided in the earlier device and matrix 116 represents routinglines andPIPs not provided in the earlier device for interconnecting thedomains. For example, domain 104 may include an extra row (more likelyseveral rows) of logic blocks, and domain 106 may include a block of RAMmemory. Matrix 116 may include considerable additional routing lines andPIPs for improving the routability of the additional rows in domain 104and their interconnections to domains 102 and 106. The firstconfigurable domain 102 may be programmed to perform an algorithmicdecryption function, the second configurable domain 104 may beprogrammed as a microcontroller, and the third configurable domain 106combined with matrix 116 may be programmed as an addressable memory. Theconfiguration bits customize the interconnection matrix 116 between thefirst configurable domain 102 and the second configurable domain 104based on their decryption and microcontroller functions. Similarly, theconfiguration bits customize the interconnection matrix 116 between thesecond configurable domain 104 and the third configurable domain 106based on their microcontroller and memory functions. Those skilled inthe art will recognize that each configurable domain may be programmedto perform many other logic functions.

The following explanation of the first configurable domain 102 embodiedwithin an FPGA applies also to configurable domains 104 and 106. Whilethe following discussion is centered upon configuring an FPGA, thepresent invention is applicable to other types of configurable devices.

The first configurable domain 102 is preferably an FPGA-based deviceincluding a configuration memory array 118, a frame register 121 and arow shift register 122. The configuration memory array 118 includes amatrix of memory cells 124 which function, among other things, aslook-up table memory and routing selectors. While the configurationmemory array 118 is shown as an 18×18 array of memory cells 124, FPGAmemory arrays are typically much larger. Configuration memory array 118is described in detail in "The Programmable Logic Data Book," publishedby Xilinx, Inc., 1994.

The matrix of memory cells 124 is organized in regular discrete arraysto control configurable logic blocks labeled CLB, input/output blockslabeled IOB, and corner logic blocks labeled CL. The CLBs providefunctional elements for constructing a user's logic and are bounded onall four sides by either IOBs or other CLBs. The IOBs communicate databetween the FPGA's external pins (not shown) and configurableinterconnect.

The CLBs, IOBs and corner logic blocks CL are configured by shifting theconfiguration bits into the frame register 121 and then loading thecontents of frame register 121 in parallel over the connect lines 134into successive rows of the memory cells 124. The frame register 121 isa conventional serial shift register that receives sequentially clockedconfiguration bits over the input line 108. In order to facilitate thisparallel loading, a row pointer 136 in the row shift register 122sequentially references each row in the memory array 118. The row shiftregister 122 consists of pointer cells, each of which stores a logic`0`, except for of one pointer cell which stores a logic `1.` Thepointer cell storing the logic 1 is referred to as the row pointer 136.The row pointer 136 shifts sequentially through the row shift register122 starting from the top or bottom pointer cell to sequentially loadthe contents of the configuration memory array 118 on a row-by-rowbasis.

For example, during loading of the configuration memory array 118, rowpointer 136 will at some time address row 140. Pointer 136 causes thedata in the frame register 121 to be loaded into row 140, after whichpointer 136 shifts one pointer cell and points to row 138. With rowpointer 136 addressing row 138, frame register 121 shifts a next frameof configuration bits in parallel into row 138. In this manner, each rowof configuration memory array 118 is loaded with configuration bits. Inan alternative embodiment, rows may be addressed using conventionaldecoders, demultiplexers or state machines.

Each configurable domain 102, 104, 106 contains a configuration controlblock 152, 154, 156. Configuration control block 152 initializes the rowshift register 122, controls clocks (not shown) to the frame register121 and the row shift register 122, and controls the write signal (notshown) that writes data from the frame register 121 to the configurationmemory array. The configuration control block waits for the first bithaving a logic level `1` on the input line before starting itsinitialization sequence.

Once the memory array 118 has been filled with configuration bits,configuration control block 152 outputs a "FULL" signal (logic `1`) online 132. The configuration memory array 118 in each of its four cornershas a respective corner logic block 131 which performs specialfunctions, such as generating a global clock signal. Configurationcontrol block 152 may physically reside in a comer logic block CL.

After the pointer 136 in row shift register 122 has shifted out, no moreconfiguration data will be loaded into memory 118. Configuration controlblock 152 may have connections not shown from frame register 121 and rowshift register 122. In one embodiment, a logical 1 shifted out of rowshift register 122 triggers the FULL signal on line 132. The FULL signalon line 132 indicates that all configuration data have been received andstored in memory array 118. An AND gate 146 receiving signals from bothinput line 108 and FULL line 132 allows configuration data bits to passover the first overflow line 110 to the second configurable domain 104.Prom the perspective of all subsequent configurable domains 104, 106,the overflow lines 110, 112 and AND gates 148 and 150 behave just as theinput line 108 and AND gate 146.

Configuration control blocks 154 and 156 may reside within an IOB, CLB,or CL, if those elements are present in the domain, or may be placedelsewhere in the device.

FIG. 2 is a block diagram illustrating a configuration bitstream 200 forconfiguring the apparatus of FIG. 1. Configuration bitstream 200 is aserial stream of bits which includes a set of first domain configurationbits 202, a set of second domain configuration bits 204, and a set ofthird domain configuration bits 206 for programming the configurabledomains 102, 104, and 106, respectively.

In a contemplated usage of the invention, a prior generationconfigurable device, for example a single chip having only the firstconfigurable domain 102 (FIG. 1), is programmable with only the set offirst domain configuration bits 202. If it is desired to replace theprior generation device with the present generation configurable device100, the first domain configuration bits 202 may be used without changeto configure the first configurable domain of device 100. If features ofthe additional configurable domains 104, 106 are not needed, no seconddomain configuration bits 204 and no third domain configuration bits 206are input to device 100. Consequently memory arrays 119, 120 are notloaded with data. With only its first configurable domain 102programmed, device 100 operates the same as the prior generationconfigurable device. This provides backward compatibility between device100 and the prior generation configurable device.

Each addition of a new configurable domain increases the functionalityof device 100. As functionality is added to device 100, the set ofsecond domain configuration bits 204 through the set of third domainconfiguration bits 206 may be concatenated to the set of first domainconfiguration bits to expand the configuration bitstream 200 easily.

FIG. 3 is a block diagram illustrating an alternative embodiment of anapparatus for making the configuration bitstream of a prior generationconfigurable device compatible with a present generation configurabledevice. Device 300 includes a first configurable domain 302, a secondconfigurable domain 304, an input line 308, a first overflow line 310, asecond overflow line 312, and an interconnection matrix 316 which areintercoupled and function similarly to the corresponding elements ofFIG. 1. Where elements correspond, they are given similar referencenumbers. The differences between the device 100 and the device 300 areas follows.

The configuration bits received by configurable domain 302 functionsimilarly to those received by configurable domain 102. However, device300 utilizes one "no extension" bit referred to as "NO₋₋ EXT" in theconfiguration bitstream to indicate whether a successive configurabledomain 304, etc., is to be loaded with configuration data. The NO₋₋ EXTbit is a logic level 0 if the successive configurable domain is to beconfigured and is a logic level 1 if not.

To make the configuration bitstream of a prior generation configurabledevice compatible with a present generation configurable device 300, theconfiguration bitstream for the prior generation device is provided withan extra bit. The extra bit is the NO₋₋ EXT bit. In replacing the priorgeneration device with the present generation device, the configurationbitstream of the prior generation device may be used without change ifadditional functionality of the present generation device is notrequired by setting the NO₋₋ EXT bit to logic level 1. If the addedfunctionality is desired, the NO₋₋ EXT bit is changed to logic level 0and an additional configuration bitstream is concatenated to theoriginal bitstream.

Device 300 operates with the NO--EXT bit as follows. The NO₋₋ EXT bit isloaded into one of the memory cells of the domain 302. If the secondconfigurable domain 304 is not to be filled with configuration bits, theNO₋₋ EXT bit is set to logic level `1`, otherwise it is set to logiclevel `0`. Configuration control block 352 in domain 302 sends a "FULL"signal over line 332 and memory 318 sends the NO₋₋ EXT bit over signalline 342. If the domain 302 has been fully programmed with configurationbits, then the FULL signal is set to logic level `1`, otherwise it isset to logic level `0`.

Lines 332 and 342 are input to AND gate 374, whose output is input to ORgate 378. The output of OR gate 378 and input line 308 are coupled tothe inputs of AND gate 348, whose output is applied to the secondoverflow line 312. If the FULL and NO₋₋ EXT signals are set to logiclevel `1`, then AND gate 374 outputs a logic level `1` signal to OR gate378. In response, OR gate 378 outputs a logic level `1` signal to ANDgate 348, thereby allowing any remaining configuration bits to betransmitted from the input line 308 to the second overflow line 312.

Lines 332 and (with an inverter) 342 are also coupled to the input ofAND gate 376. The output of AND gate 376 along with the signal on inputline 308 are input to AND gate 346, whose output is coupled to the firstoverflow line 310. If the FULL signal on line 332 is set to logic level`1` and the NO₋₋ EXT bit on line 342 is set to logic level `0`, then ANDgate 376 outputs a `1` signal to AND gate 346 which allows any remainingconfiguration bits to be transmitted from the input line 308 over thefirst overflow line 310 to the second configurable domain 304.

If AND gate 346 permits transmission of configuration bits to the secondconfigurable domain 304, then once the second configurable domain 304has been filled with configuration bits, the FULL signal on line 326 isset to logic level `1`. Line 326 is coupled to an input of OR gate 378and if a logic level `1` is present on line 326, OR gate 378 outputs alogic level 1 signal to AND gate 348, which then transmits any extraconfiguration bits from input line 308 to the second overflow line 312.

FIG. 4 is a block diagram illustrating a configuration bitstream forconfiguring the device of FIG. 3. The configuration bitstream 400comprises a set of first domain configuration bits 402, a first domainNO₋₋ EXT bit 404, and a set of second domain configuration bits 406. Theconfiguration bitstream 400 is a serial set of bits for programming atleast the first configurable domain 302, and, optionally, the secondconfigurable domain 304. The set of first domain configuration bits 402programs the first configurable domain 302, and the set of second domainconfiguration bits 406 programs the second configurable domain 304 onlyif the NO₋₋ EXT bit 404 is set to logic level `0`. If the NO₋₋ EXT bit404 is set to logic level `1`, any second domain configuration bits 406are transmitted on the second overflow line 312.

To further illustrate how bitstream compatibility is maintained from aprior generation device to a present generation device, consider thefollowing scenario. An application has a pair of daisy-chainedconfigurable devices: a prior generation configurable device and asecond configurable device whose generation is immaterial for thepurpose of this discussion. The bitstream to program the pair of devicesconsists of a set of configuration bits for the prior generation devicefollowed by a set of configuration bits for the second device. If theapplication eventually requires replacement of the prior generationdevice with the present generation device (e.g., 300) where newfunctionality of the present generation device is not required, theoriginal bitstream may continue to be used. The NO₋₋ EXT bit having alogic level `1` prevents configuration bits intended for the seconddevice from being loaded in the second configurable domain 304 of thepresent generation device 300, and instead causes the bits to be passedon line 312 to the second device.

FIG. 5 is a block diagram illustrating a third alternative embodiment ofan apparatus for making the configuration bitstream of a priorgeneration configurable device compatible with a present generationconfigurable device. Device 500 includes a data input line 508, anoverflow line 510, a first frame shift register 521a, a second frameshift register 521b, a first row shift register 522a, a second row shiftregister 522b, a first configuration memory array 518a interleaved witha second configuration memory array 518b, a first set of data lines534a, a second set of data lines 534b, FULL lines 532a and 532b, ANDgates 562 and 546, and configuration control blocks 552a and 552b.

Configuration bits input on line 508 are routed to configuration controlblock 552a and to the first frame shift register 521a for loading viathe first set of data lines 534a into the first configuration memoryarray 518a. The first row shift register 522a functions similarly to therow shift register 122 of FIG. 1. Once the first configuration memoryarray 518a has been fully loaded the FULLa signal on line 532a is set tologic level `1`.

The FULLa signal line 532a and the data input line 508 are connected tothe inputs of AND gate 562 to route additional configuration bits to thesecond frame shift register 521b and to configuration control block 552bwhen the FULLa signal line 532a carries a logic level `1`. Theconfiguration control block 552b initializes the second row shiftregister 522b. The second configuration memory array 518b is loaded withbits via data lines 534b from the second frame shift register 521b ascontrolled by row shift register 522b in a manner similar to the loadingof the first configuration memory array 518a. After the secondconfiguration memory array 518b has been fully loaded, the FULLb signalon line 532b is set to logic level `1`.

The FULLb signal on line 532b and the data input signal on line 508 areconnected to inputs of AND gate 546 so that when the FULLb signal online 532b carries a logic level `1` additional configuration bits willbe transmitted on overflow line 510.

The third alternative embodiment 500 interleaves the secondconfiguration memory array 518b with the first configuration memoryarray 518a to maintain bitstream compatibility from a prior generationconfigurable device (not shown) to a present generation configurabledevice when additional functionality is added to a configurable device.If only the first configuration memory array 518a is filled, then thedevice 500 functions the same as a prior generation configurable devicehaving only one configuration memory array.

Another embodiment not shown combines the interleaving of FIG. 5 withthe NO₋₋ EXT option of FIG. 3 so that a domain such as that comprisingmemory cells 518b of FIG. 5 can be skipped and subsequent devices thatare accessed on overflow line 510 can be programmed.

FIG. 6 is a flowchart of steps in a preferred method for making theconfiguration bitstream of a prior generation configurable devicecompatible with a present generation configurable device. The methodbegins at step 600 where a set of configurable domains 102, 104, 106(FIG. 1) are provided in a first configurable device 100. At step 602, aconfiguration bitstream 200 (FIG. 2) is input to the configurable device100. At step 604, a frame of bits from bit stream 200 is loaded into afirst configurable domain 102. At step 606, if the first configurabledomain 102 is not full, then the method returns to step 604. Otherwise,the method proceeds to step 608.

At step 608, any bits which were not loaded into a prior configurabledomain are transmitted as overflow bits to a next configurable domaininside the first configurable device 100. Step 610 loads frames ofoverflow bits into the next configurable domain. At step 612, if thenext configurable domain is not full the method returns to step 610, andotherwise proceeds to step 614. If in step 614 there are any moreconfigurable domains to load within the first configurable device 100,the method returns to step 608, and otherwise proceeds to step 618. Atstep 618, any bits which were not used to program the first configurabledevice 100 are overflow bits to a next configurable device or devices.After step 618, the method is complete.

FIG. 7 is a flowchart of an alternative method for making theconfiguration bitstream of a prior generation configurable devicecompatible with a present generation configurable device. Thealternative method begins at step 700 where a set of interconnectedconfigurable domains 302, 304 (FIG. 3) are provided within a firstconfigurable device 300. At step 702, a configuration bitstream 400having a NO₋₋ EXT bit 404 (FIG. 4) is input to configurable device 300.Step 704 loads a frame of bits from the configuration bit stream 400into a first configurable domain 302. At step 706, if the firstconfigurable domain 302 is not full the method returns to step 704, andotherwise proceeds to step 708.

If the NO₋₋ EXT bit 404 is set to logic level true (`1`), step 708directs the method to step 718. Otherwise, the method continues at step710. Step 710 transmits overflow bits to a next configurable domainwithin the first configurable device 300. The next configurable domainis loaded with a frame of overflow bits at step 712. If the nextconfigurable domain is not full, step 714 returns the method to step712. Otherwise, the method proceeds to step 718.

Any bits which were not used to program the first configurable device300 are transmitted as overflow bits to a next configurable device.After step 718, the method is complete.

The embodiments described herein are for purposes of illustration andare not intended to be limiting. Therefore, those skilled in the artwill recognize that other embodiments could be practiced withoutdeparting from the scope and spirit of the invention as described by theclaims set forth below.

I claim:
 1. A configurable electronic device which is compatible with aprior generation configurable electronic device, the prior generationconfigurable device being configurable by a first bitstream, theconfigurable electronic device comprising:a first configurable domainwhich is integrated in the configurable device and configurable by thefirst bitstream; a second configurable domain which is integrated in theconfigurable device and optionally configurable by an optional secondbitstream concatenated to the first bitstream; and configuration meansfor loading the first bitstream into said first configurable domain andfor loading said second configurable domain with the optional secondbitstream; and signal means coupled to said configuration means forindicating when the first bitstream has been loaded into said firstconfigurable domain.
 2. The configurable electronic device of claim 1,further comprising:control means coupled to said signal means andcoupled to said second configurable domain for loading said secondbitstream into said second configurable domain in response to saidsignal means indicating said first configurable domain has been loaded.3. The configurable electronic device of claim 1, furthercomprising:interconnection means for interconnecting the secondconfigurable domain with the first configurable domain in response tothe optional second bitstream.
 4. A configurable electronic device whichis compatible with a prior generation configurable electronic device,the prior generation configurable device being configurable by a firstbitstream, the configurable electronic device comprising:a firstconfigurable domain which is integrated in the configurable device andconfigurable by the first bitstream, said first configurable domainhaving:a first memory array for storing the first bitstream; a firstshift register coupled to said first memory array for receiving thefirst bitstream and; first signal means for indicating when the firstbitstream has been loaded into said first memory array; a secondconfigurable domain which is integrated in the configurable device andoptionally configurable by an optional second bitstream concatenated tothe first bitstream, said second configurable domain having:a secondmemory array for storing the optional second bitstream; and a secondshift register coupled to said second memory array for receiving theoptional second bitstream; a first logic gate having a first inputcoupled to said first signal means, a second input coupled to receivethe input configuration bitstream, and an output coupled to said secondshift register, whereby the optional second bitstream is transmitted tosaid second configurable domain when the first bitstream has been loadedinto said first configurable domain.
 5. The configurable electronicdevice of claim 4, wherein:said second configurable domain has a secondsignal means for indicating when the optional second bitstream has beenloaded into said second memory array; and the configurable electronicdevice further comprises a second logic gate having a first inputcoupled to said second signal means, a second input coupled to receivethe output of said first logic gate, and an output coupled to anadditional configurable domain, whereby an additional bitstream which isconcatenated to the second bitstream is transmitted to an additionalconfigurable domain when the second bitstream has been loaded into saidsecond configurable domain.
 6. The configurable electronic device ofclaim 4, further comprising:interconnection means for interconnectingthe second configurable domain with the first configurable domain inresponse to the optional second bitstream.
 7. A configurable electronicdevice which is compatible with a prior generation configurableelectronic device, the prior generation configurable device beingconfigurable by a first bitstream, the configurable electronic devicecomprising:a first configurable domain which is integrated in theconfigurable device and configurable by the first bitstream; firstconfiguration means for loading the first bitstream into said firstconfigurable domain, the first bitstream having an extension code forindicating whether another configurable domain within the configurabledevice is to receive bits which follow the first bitstream; a secondconfigurable domain which is integrated in the configurable device andoptionally configurable by an optional second bitstream concatenated tothe first bitstream; second configuration means coupled to said secondconfigurable domain and coupled to said first configuration means forloading said second configurable domain with said second bitstream; andbypass means coupled to said first configuration means for receivingsaid extension code and coupled to said second configuration means fortransmitting said second bitstream to said second configuration means ifdirected by said extension code, whereby said second bitstream mayoptionally bypass said second configurable domain.
 8. The configurableelectronic device of claim 7, further comprising:first signal meanscoupled to said first configuration means for indicating when the firstbitstream has been loaded into said first configurable domain; secondsignal means coupled to said second configuration means for indicatingwhen said optional second bitstream has been loaded into said secondconfigurable domain; and overflow means, coupled to said first signalmeans and said second signal means, for transmitting a third bit streamwhich is concatenated to the optional second bit stream of theconfigurable device when said first bitstream has been loaded into saidfirst configurable domain and said second bitstream has been loaded intosaid second configurable domain, whereby said third bit stream is routedto a daisy-chained configurable device.
 9. The configurable electronicdevice of claim 7, further comprising:interconnection means forinterconnecting the second configurable domain with the firstconfigurable domain in response to the optional second bitstream.
 10. Aconfigurable electronic device which is compatible with a priorgeneration configurable electronic device, the prior generationconfigurable device being configurable by a first bitstream, theconfigurable electronic device comprising:a first configurable domainwhich is integrated in the configurable device and configurable by thefirst bitstream, the first bitstream having an extension code forindicating whether another configurable domain within the configurabledevice is to receive bits which follow the first bitstream, said firstconfigurable domain having:a first memory array for storing the firstbitstream; a first shift register for receiving the first bitstream andcoupled to said first memory array; and first signal means forindicating when the first bitstream has been loaded into said firstmemory array and when the extension code indicates that bits whichfollow the first bitstream are to be transmitted to another configurabledomain; a second configurable domain which is integrated in theconfigurable device and optionally configurable by an optional secondbitstream concatenated to the first bitstream, said second configurabledomain having:a second memory array for storing the optional secondbitstream; and a second shift register for receiving the optional secondbitstream and coupled to said second memory array; a first logic gatehaving a first input coupled to said first signal means, a second inputcoupled to receive the input configuration bitstream, and an outputcoupled to said second shift register, whereby the optional secondbitstream is transmitted to said second configurable domain when thefirst bitstream has been loaded into said first configurable domain andthe extension code indicates another configurable domain within theconfigurable device is to receive bits which follow the first bitstream.11. The configurable electronic device of claim 10, further comprisingbypass means coupled to said first signal means for receiving the inputbitstream and transmitting the second bitstream to another configurabledomain if said first configurable has been loaded with the firstbitstream and the extension code indicates that said second configurabledomain should be bypassed.
 12. A method for configuring a configurableelectronic device with a first bitstream which was used to configure aprior generation configurable device, the configurable device having afirst configurable domain and a second configurable domain, the methodcomprising the steps of:loading the first bitstream into a firstconfigurable domain in the configurable device; detecting when the firstbitstream has been loaded into the first configurable domain; andloading a second bitstream into a second configurable domain in theconfigurable device if a second bitstream is concatenated to the firstbitstream.
 13. The method of claim 12, further comprising the step ofinterconnecting the first configurable domain and the secondconfigurable domain in response to said second bitstream.
 14. A methodfor configuring a configurable electronic device with a firstconfiguration bitstream which was used to configure a prior generationconfigurable device, the configurable device having a first configurabledomain and a second configurable domain, the method comprising the stepsof:loading the first bitstream into the first configurable domain, thefirst bitstream having an extension code for indicating whether thesecond configurable domain is to receive bits which follow the firstbitstream; and if a second bitstream is concatenated to the firstbitstream and the extension code indicates that the second configurabledomain is to be loaded with bits which follow the first bitstream,loading the second configurable domain.
 15. The method of claim 14further comprising the step of transmitting the second bitstream of theconfigurable device if the second bitstream is concatenated to the firstbitstream and the extension code indicates that the second configurabledomain is not to be loaded with bits which follow the first bitstream,whereby the second configurable domain is bypassed in loadingconfiguration data.
 16. The method of claim 14 further comprising thestep of interconnecting the first configurable domain with the secondconfigurable domain in response to the second bitstream if the extensioncode indicates that the second configurable domain is to be loaded withbits which follow the first bitstream.